Semiconductor company Ingonyama has written an article introducing a versatile and programmable hardware accelerator called the Zero Knowledge Processing Unit (ZPU) for designing zero-knowledge cryptography. The article discusses the architecture and design considerations and compares it to Zprize winners PipeZK, RPU, and TREBUCHET.
The Zero Knowledge Processing Unit (ZPU) is a multi-purpose hardware accelerator designed to meet the demands of zero-knowledge processing. The ZPU is built on an instruction set architecture (ISA) that allows for programmability, enabling it to adapt to rapidly evolving encryption algorithms. The ZPU features an interconnect network of processing elements (PEs) that support large-word modularity operations natively. The PE’s core structure is inspired by MAC engines, a fundamental processing element in digital signal processing (DSP) and other computing systems. The PE’s arithmetic logic unit uses modular arithmetic and is customized to support common operations in ZK algorithms.
ZPU Performance Evaluation: NTT butterfly operations are performed every clock cycle and according to our calculations, only a configuration of 72 PEs running at a GPU frequency of 1.305 GHz is sufficient to match the performance of the GPU category winner in MSM operations in Zprize. Compared to the efficient pipeline accelerator PipeZK, only a configuration of 17 PEs running at a frequency of 300MHz is sufficient to match the performance of PipeZK’s MSM operations. Additionally, compared to RPU, our calculations indicate that to achieve the performance of RPU’s optimal configuration when computing 128-bit elements 64K NTT, we need approximately 23 PEs running at RPU’s 1.68 GHz frequency.
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Reference: https://medium.com/@ingonyama/zpu-the-zero-knowledge-processing-unit-f886a48e00e0
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